IMPLEMENTATION OF EFFICIENT FIR FILTER

Abstract

Abstract.  In this paper, Design and implementation of FIR Filter done by using Han-Carlson Adder. To design Filter different blocks required which are Adders, Multipliers, and Delay elements. FIR Filters are easy to design and are less power consuming. Here for designing of multiplier Han-Carlson Adder used and the filter is designed using proposed multiplier and delay element( D-flip flop).[1] The reason of selecting Han-Carlson adder is their performance, it is one of the fastest adders as compare to other adders on other hand its circuit is complex but it has given efficient performance as compare to others adder. Our main focus is on the parameter of adders, Multiplier and Fir Filters such as Power, LUT utilization, area and delay to make an efficient FIR Filters using Vedic mathematics.[2] The proposed FIR Filter has designed and simulate with help Verilog HDL codes and their circuit diagram and Simulation result of the filter has synthesized on Xilinx Tool and Questa Sim.